BIOS Setup




Глава 06


4.3. Кэширование памяти
Ext BIOS EC00-EFFF
Cache Extended Memory Area
Cache C800-CBFF
Cache DRAM Memory Area
DC00 - DFFF
640KB to 1MB Cacheability
Async L2 Cache Leadoff
Cache Burst Read Cycle
Cache Rd+CPU Wt Pipeline
Cache Timing
CPU External Cache
CPU Internal Cache
Иллюстрация 1
External Cache Write Policy
Internal Cache WB or WT
L2 Cache Allocation
L2 Cache Banks
X 2-Bank L2 Cache Speed,
L2 Cache Burst Addressing
L2 Cache Cacheable Size
L2 Cache Size
L2 Cache Timing
L2 Cacheing Control
Memory above 16MB Cacheable
Non-Cacheable Block-1 Size
Non-Cacheable Block-1 Base
Non-Cacheable Block-2 Base
Block 1 Size
PCI Cycle Cache Hit WS
PCI Master Read Caching
Pipeline
Pipeline Cache Timing
Shadow Memory Cacheable
DC00,16K Shadow
SRAM Back-to-Back
SRAM Type
Sustained 3T Write
SYNC SRAM Support
System BIOS Cacheable
Tag Compare Wait States
Tag Option
Tag Ram Includes Dirty
Tag/Dirty Implement
X Dirty pin selection
USWC Write Posting
Video BIOS Cacheable
Video Memory Cache Mode
Иллюстрация 2
Video RAM Cacheable
Weak Write Ordering








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